1. Field of the Invention
The present invention relates to a method for forming a CMOS transistor, and more particularly, relates to a method for forming shallow junctions in a CMOS transistor.
2. Description of the Related Art
With advances in the semiconductor technology, the dimensions of the integrated circuit devices have shrunk to the deep sub-micron range. Some problems are incurred due to the process of scaling down. The most common problem is the short channel effect. In deep sub-micron CMOS technology, shallow junctions with low resistance values are required to alleviate or avoid the influences of short channel effect. However, based on experimental results, it is almost impossible to obtain a p-type junction of depth less than 500 .ANG. via ion implantation. Therefore, other methods, such as the, solid state diffusion method or gas diffusion method, are used instead. In the solid state diffusion method, borosilicate glass (BSG) is commonly used as a p-type diffusion source.
FIG. 1A to FIG. 1D illustrate a process of fabricating shallow junctions in a COMS transistor by using BSG as a diffusion source. A semiconductor substrate 1 having an n-well region 2, a p-well region 3, and field oxide layer 4 is provided. Polysilicon gates 5 and 6 are also formed over the n-well region 2 and p-well region 3 respectively. First, a photoresist layer 7 is formed over the n-well region 2, and then arsenic ion implantation 8 is carried out to form n-type shallow junctions 9 in the p-well region 3, as shown in FIG. 1A. After removing the photoresist layer 7, an oxide layer 10 is deposited over the n-well region 2, p-well region 3, field oxide layer 4, and gates 5 and 6. The oxide layer 10 is partially etched such that only the portion over the p-well region 3 is reversed, as shown in FIG. 1B. Next, a BSG layer 11 is deposited and etched back, and the result is depicted in FIG. 1C. Finally, p-type ion implantation and n-type ion implantation are carried out to the n-well region 2 and the p-well region 3 respectively. Then, a thermal process is carried out to form source/drain regions 12, 13 in the CMOS transistor, as shown in FIG. 1D. During the thermal process, boron ions are diffused from the BSG layer 11 and thus form the shallow junctions 14 in the n-well region. In p-well region 3, because oxide layers 10 are formed between BSG layer 11 and p-well region 3, the n-type shallow junction 9 can be kept intact.
Although the above method can fabricate shallow junctions in a CMOS transistor, some drawbacks are inevitable. The formation of the BSG layer is by global deposition, and the n-type transistor not requiring p-type shallow junction must be protected by an oxide layer. Consequently, an additional mask is required to form the oxide layer. Otherwise, the n-type transistors must be fabricated first, followed by forming the p-type shallow junctions in p-type transistors via the solid-state diffusion method. However, this process is more complicated and costly.